Pipelined Microarchitecture for VTA With Circuit and Instruction Co-Optimization

Tensor virtual machine–versatile tensor accelerator (TVM–VTA) stack is an end-to-end deep neural network (DNN) accelerator template known for its high reconfigurability and flexibility. However, baseline TVM–VTA accelerator templates may introduce pipeline and scheduling inefficiencies. Pipelined VTA (PVTA) focuses on the specific execution bottlenecks of the TVM–VTA stack and develops a pipeline-oriented solution across microarchitecture and instruction flow. The proposed architecture redesigns the GEMM and ALU pipelines, instruction flow, LOAD module, and dual-thread dependency mechanism, while maintaining compatibility with the existing software-hardware stack. Implemented on Xilinx ZCU104 FPGA, the proposed PVTA achieves a DSP efficiency of 0.564, delivering 3.9× and 2.54× speedups over the original VTA on ResNet-50 and YOLOv3, with final throughputs of 29.2 and 7.25 fps, respectively. These improvements demonstrate the effectiveness of pipeline-focused optimizations in enhancing VTA’s performance for end-to-end DNN acceleration. Evaluation against representative VTA-based designs shows that PVTA attains the highest reported end-to-end speedup within the VTA framework. Compared to other leading architectures, the proposed approach achieves comparable or higher performance while preserving a high degree of flexibility, enabling VTA to evolve from a research template into a competitive, high-performance end-to-end accelerator.