TY - GEN
T1 - Optimum double-layer spiral inductor on silicon substrate designed for monolithic buck converters
AU - Li, Qing Hua
AU - Geng, Li
AU - Shao, Zhi Biao
PY - 2005
Y1 - 2005
N2 - An optimum design strategy of double-layer square spiral inductor for the monolithic low-voltage, low-power buck converter operating at 100MHz is presented. After optimization using 0.35μ.m standard CMOS technology, the inductor with inductance of 24.74nH, Q factor of 8.43 and occupied area 0.19 square millimeters is achieved. A simple circuit model is given to simulate the performance of the buck converter. From the simulation results, the designed double-layer spiral inductor can satisfy the requirement.
AB - An optimum design strategy of double-layer square spiral inductor for the monolithic low-voltage, low-power buck converter operating at 100MHz is presented. After optimization using 0.35μ.m standard CMOS technology, the inductor with inductance of 24.74nH, Q factor of 8.43 and occupied area 0.19 square millimeters is achieved. A simple circuit model is given to simulate the performance of the buck converter. From the simulation results, the designed double-layer spiral inductor can satisfy the requirement.
UR - https://www.scopus.com/pages/publications/33847118643
U2 - 10.1109/APMC.2005.1606749
DO - 10.1109/APMC.2005.1606749
M3 - 会议稿件
AN - SCOPUS:33847118643
SN - 078039433X
SN - 9780780394339
T3 - Asia-Pacific Microwave Conference Proceedings, APMC
SP - 4
EP - 7
BT - APMC 2005
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - APMC 2005: Asia-Pacific Microwave Conference 2005
Y2 - 4 December 2005 through 7 December 2005
ER -