TY - GEN
T1 - Modeling the gate driver IC for GaN transistor
T2 - 33rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2018
AU - Xie, Ruiliang
AU - Xu, Guangzhao
AU - Yang, Xu
AU - Tang, Gaofei
AU - Wei, Jin
AU - Tian, Yidong
AU - Zhang, Feng
AU - Chen, Wenjie
AU - Wang, Laili
AU - Chen, Kevin J.
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/4/18
Y1 - 2018/4/18
N2 - During the switching performance evaluation for Si-based power devices, the gate driver IC's are commonly neglected because of Si device's slow switching speed. GaN transistors, with much smaller intrinsic capacitances, would enable faster switching speed and higher switching frequency. Consequently, the gate driver would largely impact the switching performance as well as the dead-time of the GaN transistor. In previous works, however, the gate driver IC used to drive GaN transistor have been ignored in circuit simulation, leading to lower modeling accuracy. In consideration of the lack of gate driver IC's critical design parameters, along with less familiarity of power electronics engineer/researcher with the semiconductor technologies, the gate driver IC could be regarded as a 'black-box'. Despite the difficulty in directly performing measurements inside the driver chip package, a black-box modeling method could be proposed. Based on the measured terminal current/voltage signals in a typical gate drive scheme, the I-V characteristics of the PMOS in the totem-pole topology could be extracted. With respect to the C-V curves, the characteristics of a discrete Si MOSFET with comparable voltage/current rating could be introduced. Taking into account the operating principle of the totem-pole topology, a circuit-level model could be established. Consequently, the simulated waveforms are in reasonable agreements with the testing results. Taking advantages of the proposed black-box modeling method, the switching transient waveforms as well as the dead-time of GaN transistor could be more accurately evaluated.
AB - During the switching performance evaluation for Si-based power devices, the gate driver IC's are commonly neglected because of Si device's slow switching speed. GaN transistors, with much smaller intrinsic capacitances, would enable faster switching speed and higher switching frequency. Consequently, the gate driver would largely impact the switching performance as well as the dead-time of the GaN transistor. In previous works, however, the gate driver IC used to drive GaN transistor have been ignored in circuit simulation, leading to lower modeling accuracy. In consideration of the lack of gate driver IC's critical design parameters, along with less familiarity of power electronics engineer/researcher with the semiconductor technologies, the gate driver IC could be regarded as a 'black-box'. Despite the difficulty in directly performing measurements inside the driver chip package, a black-box modeling method could be proposed. Based on the measured terminal current/voltage signals in a typical gate drive scheme, the I-V characteristics of the PMOS in the totem-pole topology could be extracted. With respect to the C-V curves, the characteristics of a discrete Si MOSFET with comparable voltage/current rating could be introduced. Taking into account the operating principle of the totem-pole topology, a circuit-level model could be established. Consequently, the simulated waveforms are in reasonable agreements with the testing results. Taking advantages of the proposed black-box modeling method, the switching transient waveforms as well as the dead-time of GaN transistor could be more accurately evaluated.
KW - Black-box approach
KW - GaN transistor
KW - Gate driver IC
KW - Modeling
UR - https://www.scopus.com/pages/publications/85046963601
U2 - 10.1109/APEC.2018.8341429
DO - 10.1109/APEC.2018.8341429
M3 - 会议稿件
AN - SCOPUS:85046963601
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 2900
EP - 2904
BT - APEC 2018 - 33rd Annual IEEE Applied Power Electronics Conference and Exposition
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 4 March 2018 through 8 March 2018
ER -