Methodology for avoidance of ratcheting-induced stable cracking (RISC) in microelectronic devices

A typical microelectronic device contains a silicon die in a package encapsulated with an epoxy. This polymer and various inorganic materials on the die, such as metal interconnects and ceramic passivation films, have dissimilar coefficients of thermal expansion (CTEs). When such a device is subject to a change in temperature, the mismatch in the CTEs deforms the materials. In particular, as temperature cycles, the plastic deformation in a metal interconnect may accumulate incrementally, a phenomenon known as ratcheting plastic deformation. Ratcheting in the metal film may induce large stresses in an overlaying ceramic film, causing cracks to initiate and grow stably cycle by cycle. In this paper, such ratcheting-induced stable cracking (RISC) is studied using a simplified three-layer model. We describe conditions under which ratcheting will occur in the metal layer, predict the number of cycles for the crack to initiate in the ceramic film, and discuss strategies to avoid RISC in design.