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Magellan: A High-Performance Loop-Guided Prefetcher for Indirect Memory Access

  • Gelin Fu
  • , Tian Xia
  • , Mingzhuo Yin
  • , Prashant J. Nair
  • , Mieszko Lis
  • , Pengju Ren
  • Xi'an Jiaotong University
  • University of British Columbia

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Graph analytics and sparse linear algebra applications heavily rely on indirect memory access (IMA). IMAs are characterized by poor temporal and spatial locality, which causes frequent high-latency DRAM accesses. While dedicated hardware prefetchers for IMA have been explored, they target narrow access patterns and tend to introduce significant hardware complexity. Software prefetching offers a promising alternative, leveraging compiler analysis to prefetch indirection patterns. However, existing software prefetchers struggle with sparse applications due to limited loop iterations and complex IMA patterns across nested loops. We propose Magellan, a novel loop-guided software prefetcher designed to detect and schedule IMA prefetches efficiently. Magellan introduces two key innovations: (1) extracting dependence graphs across loop levels to detect complex IMA patterns and (2) capturing inner-outer loop semantics to prefetch for both current and future iterations. We evaluate Magellan on 14 memory-intensive benchmarks using real-world datasets from social networks and web graphs. Compared to the best existing IMA software prefetcher, Magellan reduces cache misses by 25% and dynamic instruction counts by 14% on average. This results in a 1.14× average speedup, with performance gains of up to 1.41×.

Original languageEnglish
Title of host publicationISCA 2025 - Proceedings of the 52nd Annual International Symposium on Computer Architecture
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages601-615
Number of pages15
ISBN (Electronic)9798400712616
DOIs
StatePublished - 21 Jun 2025
Event52nd Annual International Symposium on Computer Architecture, ISCA 2025 - Tokyo, Japan
Duration: 21 Jun 202525 Jun 2025

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897
ISSN (Electronic)2575-713X

Conference

Conference52nd Annual International Symposium on Computer Architecture, ISCA 2025
Country/TerritoryJapan
CityTokyo
Period21/06/2525/06/25

Keywords

  • Indirect Memory Access
  • Memory Hierarchy
  • Software Prefetcher

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