@inproceedings{6d60138c4c8b4b6ea625438033c0c258,
title = "Low-power and high-speed VLSI architecture of 2-D DWT for JPEG2000",
abstract = "A low-power, high-speed and minimum-area architecture which performs two-dimension forward and inverse discrete wavelet transform (DWT) for JPEG2000 is proposed by using a line-based and lifting scheme. It consists of one row processor and one column processor. And the row processor which is time-multiplexed performs in parallel with the column processor. Optimized shift-add operations are substituted for multiplications, and edge extension is implemented by embedded circuit. The whole architecture is optimized in the pipeline design way to speed up and achieve higher hardware utilization. On EP1S25, two pixels per clock cycle can be encoded at 100MHz. Only 25\% of total area of EP1S25 is needed for multilevel decomposition. The architecture can be used as a compact and independent IP core for JPEG2000 VLSI implementation and various real-time image/video applications.",
keywords = "2-D DWT, JPEG2000, Lifting Scheme, Parallel Architecture",
author = "Xuguang Lan and Nanning Zheng and Yuehu Liu",
year = "2004",
language = "英语",
isbn = "0780385276",
series = "2004 IEEE International Symposium on Consumer Electronics - Proceedings",
pages = "110--113",
booktitle = "2004 IEEE International Symposium on Consumer Electronics - Proceedings",
note = "2004 IEEE International Symposium on Consumer Electronics - Proceedings ; Conference date: 01-09-2004 Through 03-09-2004",
}