@inproceedings{f7b775cbb3084c8381476bd133faa2ff,
title = "Laminated Busbar Design for 10kV SiC MOSFET Module",
abstract = "This paper proposes a low-inductance laminated busbar with an integrated DC-link capacitor bank for 10 kV/125 A SiC half-bridge modules. The busbar system comprises two optimized sections: a power module interconnection busbar that achieves low parasitic inductance (14.41 nH with the upper switch on and 9.59 nH with the lower switch on) through mutually canceling topologies; and a capacitor bank busbar arranged in a 2P6S configuration using TDK B25620 capacitors, exhibiting a loop inductance of 13.70 nH. COMSOL electrostatic simulations confirm the dielectric integrity of the design, revealing a maximum surface electric field strength of 42.19 kV/mm at critical interfaces, which is only 21.4\% of the 197 kV/mm breakdown strength of the polyimide insulation material. Double-pulse testing demonstrates excellent transient performance, validating the overall effectiveness of the proposed busbar system.",
keywords = "DC-link Capacitor, Laminated Busbar, Parasitic Parameter, SiC MOSFET Module",
author = "Xiaoyan Zhao and Yong Chen and Xu Cheng and Xuehong Ma and Yanqun Liao and Xiaotian Zhang and Fan Zhang",
note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 IEEE 3rd International Power Electronics and Application Symposium, PEAS 2025 ; Conference date: 07-11-2025 Through 10-11-2025",
year = "2025",
doi = "10.1109/PEAS66638.2025.11403677",
language = "英语",
series = "IEEE PEAS 2025 - 2025 IEEE 3rd International Power Electronics and Application Symposium - Conference Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1837--1841",
booktitle = "IEEE PEAS 2025 - 2025 IEEE 3rd International Power Electronics and Application Symposium - Conference Proceedings",
}