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Laminated Busbar Design for 10kV SiC MOSFET Module

  • Ltd.
  • Xi'an Jiaotong University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper proposes a low-inductance laminated busbar with an integrated DC-link capacitor bank for 10 kV/125 A SiC half-bridge modules. The busbar system comprises two optimized sections: a power module interconnection busbar that achieves low parasitic inductance (14.41 nH with the upper switch on and 9.59 nH with the lower switch on) through mutually canceling topologies; and a capacitor bank busbar arranged in a 2P6S configuration using TDK B25620 capacitors, exhibiting a loop inductance of 13.70 nH. COMSOL electrostatic simulations confirm the dielectric integrity of the design, revealing a maximum surface electric field strength of 42.19 kV/mm at critical interfaces, which is only 21.4% of the 197 kV/mm breakdown strength of the polyimide insulation material. Double-pulse testing demonstrates excellent transient performance, validating the overall effectiveness of the proposed busbar system.

Original languageEnglish
Title of host publicationIEEE PEAS 2025 - 2025 IEEE 3rd International Power Electronics and Application Symposium - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1837-1841
Number of pages5
ISBN (Electronic)9798331539115
DOIs
StatePublished - 2025
Event2025 IEEE 3rd International Power Electronics and Application Symposium, PEAS 2025 - Shenzhen, China
Duration: 7 Nov 202510 Nov 2025

Publication series

NameIEEE PEAS 2025 - 2025 IEEE 3rd International Power Electronics and Application Symposium - Conference Proceedings

Conference

Conference2025 IEEE 3rd International Power Electronics and Application Symposium, PEAS 2025
Country/TerritoryChina
CityShenzhen
Period7/11/2510/11/25

Keywords

  • DC-link Capacitor
  • Laminated Busbar
  • Parasitic Parameter
  • SiC MOSFET Module

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