IMPROVED DIGITAL PHASE-LOCKED LOOP WITH ROTATIONAL FREQUENCY COMPARATOR.

In order to improve the operation of digital phase-locked loops (DPLL) in both the signal acquisition and synchronization modes, an improved digital phase-locked loop with a new rotational frequency comparator is proposed. The main feature of the proposed loop is that the phase error and the frequency offset between the input and the output of the loop are detected separately by adding the rotational frequency comparator to a conventional binary quantized loop. As a result, the improved loop can give enough freedom to be able to deal with the conflicting problem between the width of the locking-range and the ability to suppress phase jitter. The analysis of the steady-state phase error variance in the proposed loop with white Gaussian noise is based on an equivalent model. It is shown that the performance of the wider locking range is possible without effecting filtering properties.