Highly efficient and parallel VLSI architecture design for JPEG2000 of 2D-discrete wavelet transform

A highly efficient, real time and parallel pipelined architecture that performed the forward and inverse discrete wavelet transform (DWT) was proposed by using a lifting-based scheme for the filters recommended in JPEG2000. The architecture consisted of one row processor and one column processor. And they processed the signals in parallel way via the few line buffers in which the intermediate results were stored. Multiplication was substituted for shift-add operations. The whole architecture was optimized in the pipeline design way to increase the transform speed, and achieve higher hardware utilization. Finally, the architecture had been implemented in behavioral Verilog hardware description language (HDL). The architecture could be used as a compact and independent IP core for JPEG2000 VLSI implementation and various real-time image/video applications.