FPGA-based implementation of estimating saturated pixel values in RAW image

Pixel saturation is very common in the process of digital color imaging. From the perspective of optics, the CCD or CMOS achieve the maximum charge. It is important to relate an image to the light of the scene from which the image was captured. This paper presents a hardware implementation with a FPGA circuit of an algorithm to estimate saturated pixels in RAW image based on the principle of Bayesian estimation. In order to improve the accuracy of Bayesian estimation, the digital morphological dilation and connected component labeling are used to divide the saturated region. There may be three kinds of color saturation for each region. The Bayesian algorithm based on Xu' work was used to deal with 1-channel saturation. We improved the 2-channel saturation algorithm using the unsaturated channel to predict the saturation. We proposed the 3-channel saturation using surrounding pixels. Experiments show the proposed method in hardware implementation is more effective in correcting two or three color channel saturation.