FPGA-based Acceleration of Structured Light Depth Estimation

Stereo depth estimation is widely applied in computer vision and intelligent robotic systems. For real-time mobile stereo vision applications, how to efficiently design and implement stereo matching on resource-limited hardware platforms is still a grand challenge. In this paper, we propose and implement a low-power, high-resolution stereo matching hardware architecture on field-programmable gate array (FPGA) with the input of structured light camera. In order to obtain high-quality point cloud data, we present an image preprocessing module and an improved cost function for stereo matching algorithm. Furthermore, we leverage hardware description language to implement our stereo matching computing architecture and all algorithm models are evaluated on the Xilinx ZCU102 development board, which only takes about 61147 LUTs and 786 BRAMs. Compared with high-performance CPUs, the computing speed is significantly improved, 1.84 times faster than Intel i7-10700@2.90GHz, and the power consumption is only 3.915W.