Design of high efficient JPEG2000 bit-plane encoder

Focusing on the problem that the hardware complexity and low encoding efficiency exist in JPEG2000 chip implementation, a most significant bit (MSB) detection circuit was obtained through analyzing of generation mechanism of state variables, which can generate state variables in real time when the data is accessed from the code block memory. Meanwhile a column scan circuit was put into the three pass encoder, and a pipeline sequence generation circuit for run length coding and zero coding was designed in the clean-up pass coding. Finally, a bit-plane encoder with zero redundancy clock was implemented. When the method is used for implementing three-pass parallel bit-plane encoding, the operation speed is increased two times compared with the encoder realized by pixel skip and GOCS (group of column skip) the logic resources is saved about 50%, and the memory is saved about 20 kb for the size of the code block 64×64.