Design and modeling of multi-layer planar inductor for fully integrated DC/DC converters on silicon substrate

In order to improve the conversion efficiency and output current carrying capability of the fully integrated low voltage and low power DC/DC converters, a series parallel multi-layer spiral inductor based on standard 0.5μm 2P3M CMOS technology was proposed. The paralleled metals contacted by vias array increased the effective metal thickness and the series metals increased the mutual inductance between the layers. Therefore, the quality factor, the inductance in unit area and the current handling capability of the series parallel inductors were observably improved without extra technology. The developed model provides whole circuit analog analysis of fully integrated DC/CD converters with convenient basis. Closed form expressions of lumped parameters were obtained and verified with 0.5μm CMOS silicon technology. Experiment results show that the maximum quality factor is 4.2, the inductance in unit area is 83 nH per square millimeter, and the handled current is 90 mA. The model agrees well with measurements in the interesting frequency band, from 50 MHz to 400 MHz.