Design and analysis of high radix complex dividers

This paper evaluates FPGA-based high radix hardware architecture for complex division. The architecture uses the digit-recurrence algorithm with prescaling of complex operands. It efficiently executes the prescaling and recurrence procedures in shared logic resources. Thirty independent designs of different radices from 4 to 64 and input precisions from 16 to 64 are implemented in Stratix-II FPGA and results on cost and performance provide a broad space of design parameters. Moreover, methods for estimating logic resource consumption and timing performance are also given so that one could make quick evaluations on the design before any actual implementations. The proposed architecture and design can be used as standalone arithmetic units for systems-on-chip implementations, in embedded processors, or as IP for VLSI implementation in general.