@inproceedings{25f32215c75f4167b0b1e2a1b9f9cfbb,
title = "Analysis of a low-inductance packaging layout for Full-SiC power module embedding split damping",
abstract = "A novel low-inductance packaging layout for Full-SiC (Silicon Carbide) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) Module with split damping capacitors embedding inside is proposed in this paper. The 3-Demision model of the optimized layout was built and analyzed with ANSYS Q3D. The total self-inductance of the single commutation loop is only 6.2nH. Additionally, 55V voltage spike over the semiconductor on the current rate of 6717A per microsecondand remarkable current sharing characteristic are observed by LTspice simulation based on the synchronous buck circuit. Two comparative 1.2KV, 40A prototypes based on regular wire-bond structure were fabricated to verify the low inductance layout design. Experimental result of double pulse test demonstrates the validity of the design. The ultra-fast switching speed can be achieved by using the proposed layout design.",
keywords = "damping capacitor, layout, low-inductance packaging, power module, silicon carbide MOSFET",
author = "Yu Ren and Xu Yang and Fan Zhang and Linlin Tan and Xiangjun Zeng",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 31st Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2016 ; Conference date: 20-03-2016 Through 24-03-2016",
year = "2016",
month = may,
day = "10",
doi = "10.1109/APEC.2016.7468157",
language = "英语",
series = "Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "2102--2107",
booktitle = "2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016",
}