TY - GEN
T1 - An Optimal Design Method Considering Transformer Parasitic Capacitance of LLC Resonant Converters
AU - Wang, Naizeng
AU - Yang, Xu
AU - Tian, Mofan
AU - Jia, Haiyang
AU - Xu, Guangzhao
AU - Li, Zhenwei
N1 - Publisher Copyright:
© 2018 IEEJ Industry Application Society.
PY - 2018/10/22
Y1 - 2018/10/22
N2 - LLC resonant converters have been widely used in DC-DC conversion applications due to the advantages of high efficiency and high power density. There are many design methods of LLC resonant converters in former research. However, none of them take transformer parasitic capacitance into consideration. This paper proposes an optimal design method considering transformer parasitic capacitance. Firstly, a brief summary of design process is introduced. Next, a wire-wound transformer is designed and the transformer parasitic capacitance is measured. After that, the resonant parameters are selected aiming at reducing device conduction loss and satisfying gain requirement. Finally, experiments are conducted on a 400V-12V 200W GaN-based LLC resonant converter. Experimental results show that the optimal design method has good performance and the efficiency of the prototype is up to 94.2%.
AB - LLC resonant converters have been widely used in DC-DC conversion applications due to the advantages of high efficiency and high power density. There are many design methods of LLC resonant converters in former research. However, none of them take transformer parasitic capacitance into consideration. This paper proposes an optimal design method considering transformer parasitic capacitance. Firstly, a brief summary of design process is introduced. Next, a wire-wound transformer is designed and the transformer parasitic capacitance is measured. After that, the resonant parameters are selected aiming at reducing device conduction loss and satisfying gain requirement. Finally, experiments are conducted on a 400V-12V 200W GaN-based LLC resonant converter. Experimental results show that the optimal design method has good performance and the efficiency of the prototype is up to 94.2%.
KW - Dead Time
KW - LLC
KW - Optimal Design Method
KW - Transformer Parasitic Capacitance
UR - https://www.scopus.com/pages/publications/85057295625
U2 - 10.23919/IPEC.2018.8507842
DO - 10.23919/IPEC.2018.8507842
M3 - 会议稿件
AN - SCOPUS:85057295625
T3 - 2018 International Power Electronics Conference, IPEC-Niigata - ECCE Asia 2018
SP - 998
EP - 1003
BT - 2018 International Power Electronics Conference, IPEC-Niigata - ECCE Asia 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 8th International Power Electronics Conference, IPEC-Niigata - ECCE Asia 2018
Y2 - 20 May 2018 through 24 May 2018
ER -