All digital phase‐locked loop with a wide locking range

The phase‐locked loop (PLL) is used widely in communication engineering as one of the key functions. Recently, some attempts have been made to construct a digital circuit for the phase‐locked loop. However, the common problems in those attempts is that there is a trade‐off between the locking range and the output phase jitter. To solve this problem, this paper proposes a new structure for the phase‐locked loop with a wide locking range by combining the frequency control technique. For this purpose, a new digital VCO is constructed, which can vary the central frequency of the system using the programmable divider and the adder. Theoretical analyses are made for the transient behavior from the viewpoints of the locking range, frequency and phase, and the noise characteristics of the loop. The result is compared with the results of experiment and simulation. The theoretical value, experimental value and the result of simulation agreed well, indicating that the phase‐locked loop has a wide locking range.