TY - GEN
T1 - Accelerate NDN name lookup using FPGA
T2 - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
AU - Li, Yanbiao
AU - Zhang, Dafang
AU - Yu, Xian
AU - Liang, Wei
AU - Long, Jing
AU - Qiao, Hong
N1 - Publisher Copyright:
© 2014 Technical University of Munich (TUM).
PY - 2014/10/16
Y1 - 2014/10/16
N2 - Recently, Graphic Processing Units (GPUs) have been shown to be of value in supporting wire-speed name lookup in Named Data Networking (NDN). However, due to the computing model on GPU, the lookup latency is not so encouraging. In this paper, we shift the focus from GPU to Field-Programmable Gate Arrays (FPGA). We highlight three key challenges in accelerating name lookup using FPGA, and then present a scalable approach to address them. In our approach, a hierarchical and compact data structure is proposed to represent the name trie, which achieves not only effective pipeline mapping but also high memory efficiency. Further, it is finally implemented as a linear pipeline on the FPGA platform, enabling both fast lookup speed and low lookup latency. The experimental results show that our approach gains a reduction of memory cost over 90% compared with the referred GPU-based solution. Besides, the lookup throughput of our approach is almost 2.4 times higher, and the latency is up to 3 orders of magnitude lower.
AB - Recently, Graphic Processing Units (GPUs) have been shown to be of value in supporting wire-speed name lookup in Named Data Networking (NDN). However, due to the computing model on GPU, the lookup latency is not so encouraging. In this paper, we shift the focus from GPU to Field-Programmable Gate Arrays (FPGA). We highlight three key challenges in accelerating name lookup using FPGA, and then present a scalable approach to address them. In our approach, a hierarchical and compact data structure is proposed to represent the name trie, which achieves not only effective pipeline mapping but also high memory efficiency. Further, it is finally implemented as a linear pipeline on the FPGA platform, enabling both fast lookup speed and low lookup latency. The experimental results show that our approach gains a reduction of memory cost over 90% compared with the referred GPU-based solution. Besides, the lookup throughput of our approach is almost 2.4 times higher, and the latency is up to 3 orders of magnitude lower.
KW - FPGA
KW - NDN
KW - Name Lookup
KW - Pipeline
UR - https://www.scopus.com/pages/publications/84911164051
U2 - 10.1109/FPL.2014.6927403
DO - 10.1109/FPL.2014.6927403
M3 - 会议稿件
AN - SCOPUS:84911164051
T3 - Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
BT - Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 1 September 2014 through 5 September 2014
ER -