A Two-step SAR ADC with Synchronous DEM Calibration Achieving up to 15% Power Reduction

Zhechong Lan; Li Dong; Xixin Jing; Liheng Liu; Ken Li; Ziyan Shen; Zhiming Li; Li Geng

doi:10.1109/APCCAS50809.2020.9301655

A Two-step SAR ADC with Synchronous DEM Calibration Achieving up to 15% Power Reduction

Zhechong Lan
, Li Dong
, Xixin Jing
, Liheng Liu
, Ken Li
, Ziyan Shen
, Zhiming Li
, Li Geng

Faculty of Electronic and Information Engineering

Xi'an Jiaotong University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper presents a two-step 12-bit successive-approximation register (SAR) analog to-digital converter (ADC) with a synchronous Dynamic-Element-Matching (DEM) algorithm calibration. In the proposed two-step structure, the high-precision comparison is replaced by a low-power comparison in some conversion cycles, which can lower the power consumption of the ADC. The DEM calibration fits the 2-step structure very well and achieves a first-order mismatch shaping with negligible extra power loss. The proposed SAR ADC is fabricated in a standard 180 nm CMOS technology with a core area of 0.226 mm2. It consumes 9.15 μW at 200 kS/s sampling rate, resulting a power consumption reduction of 15%, and achieves a SNDR of 68.85 dB. The resulting figure of merit (FoM) is 20.13 fJ/conversion-step.

Original language	English
Title of host publication	Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020
Editors	Xuan-Tu Tran, Duy-Hieu Bui
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	11-14
Number of pages	4
ISBN (Electronic)	9781728193960
DOIs	https://doi.org/10.1109/APCCAS50809.2020.9301655
State	Published - 8 Dec 2020
Event	16th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020 - Virtual, Halong, Viet Nam Duration: 8 Dec 2020 → 10 Dec 2020

Publication series

Name	Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020

Conference

Conference	16th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020
Country/Territory	Viet Nam
City	Virtual, Halong
Period	8/12/20 → 10/12/20

Keywords

Analog to digital converter (ADC)
DEM calibration
capacitor digital to analog converter (CDAC)
successive approximation register (SAR)
two-step architecture

Access to Document

10.1109/APCCAS50809.2020.9301655

Cite this

Lan, Z., Dong, L., Jing, X., Liu, L., Li, K., Shen, Z., Li, Z., & Geng, L. (2020). A Two-step SAR ADC with Synchronous DEM Calibration Achieving up to 15% Power Reduction. In X.-T. Tran, & D.-H. Bui (Eds.), Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020 (pp. 11-14). Article 9301655 (Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS50809.2020.9301655

Lan, Zhechong ; Dong, Li ; Jing, Xixin et al. / A Two-step SAR ADC with Synchronous DEM Calibration Achieving up to 15% Power Reduction. Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020. editor / Xuan-Tu Tran ; Duy-Hieu Bui. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 11-14 (Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020).

@inproceedings{00fa1c31441f4d86ace0831730597965,

title = "A Two-step SAR ADC with Synchronous DEM Calibration Achieving up to 15\% Power Reduction",

abstract = "This paper presents a two-step 12-bit successive-approximation register (SAR) analog to-digital converter (ADC) with a synchronous Dynamic-Element-Matching (DEM) algorithm calibration. In the proposed two-step structure, the high-precision comparison is replaced by a low-power comparison in some conversion cycles, which can lower the power consumption of the ADC. The DEM calibration fits the 2-step structure very well and achieves a first-order mismatch shaping with negligible extra power loss. The proposed SAR ADC is fabricated in a standard 180 nm CMOS technology with a core area of 0.226 mm2. It consumes 9.15 μW at 200 kS/s sampling rate, resulting a power consumption reduction of 15\%, and achieves a SNDR of 68.85 dB. The resulting figure of merit (FoM) is 20.13 fJ/conversion-step.",

keywords = "Analog to digital converter (ADC), DEM calibration, capacitor digital to analog converter (CDAC), successive approximation register (SAR), two-step architecture",

author = "Zhechong Lan and Li Dong and Xixin Jing and Liheng Liu and Ken Li and Ziyan Shen and Zhiming Li and Li Geng",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 16th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020 ; Conference date: 08-12-2020 Through 10-12-2020",

year = "2020",

month = dec,

day = "8",

doi = "10.1109/APCCAS50809.2020.9301655",

language = "英语",

series = "Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "11--14",

editor = "Xuan-Tu Tran and Duy-Hieu Bui",

booktitle = "Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020",

}

Lan, Z, Dong, L, Jing, X, Liu, L, Li, K, Shen, Z, Li, Z & Geng, L 2020, A Two-step SAR ADC with Synchronous DEM Calibration Achieving up to 15% Power Reduction. in X-T Tran & D-H Bui (eds), Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020., 9301655, Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020, Institute of Electrical and Electronics Engineers Inc., pp. 11-14, 16th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020, Virtual, Halong, Viet Nam, 8/12/20. https://doi.org/10.1109/APCCAS50809.2020.9301655

A Two-step SAR ADC with Synchronous DEM Calibration Achieving up to 15% Power Reduction. / Lan, Zhechong; Dong, Li; Jing, Xixin et al.
Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020. ed. / Xuan-Tu Tran; Duy-Hieu Bui. Institute of Electrical and Electronics Engineers Inc., 2020. p. 11-14 9301655 (Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A Two-step SAR ADC with Synchronous DEM Calibration Achieving up to 15% Power Reduction

AU - Lan, Zhechong

AU - Dong, Li

AU - Jing, Xixin

AU - Liu, Liheng

AU - Li, Ken

AU - Shen, Ziyan

AU - Li, Zhiming

AU - Geng, Li

PY - 2020/12/8

Y1 - 2020/12/8

N2 - This paper presents a two-step 12-bit successive-approximation register (SAR) analog to-digital converter (ADC) with a synchronous Dynamic-Element-Matching (DEM) algorithm calibration. In the proposed two-step structure, the high-precision comparison is replaced by a low-power comparison in some conversion cycles, which can lower the power consumption of the ADC. The DEM calibration fits the 2-step structure very well and achieves a first-order mismatch shaping with negligible extra power loss. The proposed SAR ADC is fabricated in a standard 180 nm CMOS technology with a core area of 0.226 mm2. It consumes 9.15 μW at 200 kS/s sampling rate, resulting a power consumption reduction of 15%, and achieves a SNDR of 68.85 dB. The resulting figure of merit (FoM) is 20.13 fJ/conversion-step.

AB - This paper presents a two-step 12-bit successive-approximation register (SAR) analog to-digital converter (ADC) with a synchronous Dynamic-Element-Matching (DEM) algorithm calibration. In the proposed two-step structure, the high-precision comparison is replaced by a low-power comparison in some conversion cycles, which can lower the power consumption of the ADC. The DEM calibration fits the 2-step structure very well and achieves a first-order mismatch shaping with negligible extra power loss. The proposed SAR ADC is fabricated in a standard 180 nm CMOS technology with a core area of 0.226 mm2. It consumes 9.15 μW at 200 kS/s sampling rate, resulting a power consumption reduction of 15%, and achieves a SNDR of 68.85 dB. The resulting figure of merit (FoM) is 20.13 fJ/conversion-step.

KW - Analog to digital converter (ADC)

KW - DEM calibration

KW - capacitor digital to analog converter (CDAC)

KW - successive approximation register (SAR)

KW - two-step architecture

UR - https://www.scopus.com/pages/publications/85099540661

U2 - 10.1109/APCCAS50809.2020.9301655

DO - 10.1109/APCCAS50809.2020.9301655

M3 - 会议稿件

AN - SCOPUS:85099540661

T3 - Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020

SP - 11

EP - 14

BT - Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020

A2 - Tran, Xuan-Tu

A2 - Bui, Duy-Hieu

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 16th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020

Y2 - 8 December 2020 through 10 December 2020

ER -

Lan Z, Dong L, Jing X, Liu L, Li K, Shen Z et al. A Two-step SAR ADC with Synchronous DEM Calibration Achieving up to 15% Power Reduction. In Tran XT, Bui DH, editors, Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 11-14. 9301655. (Proceedings of 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020). doi: 10.1109/APCCAS50809.2020.9301655

A Two-step SAR ADC with Synchronous DEM Calibration Achieving up to 15% Power Reduction

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