A three-phase PLL algorithm based on signal reforming under distorted grid conditions

This paper proposes a novel three-phase phase-locked loop (PLL) algorithm, which focuses on the reforming of the primary signals before grid synchronization rather than improving the phase estimation methodologies. The unbalanced signals are reformed to balanced ones without damage to the phase angle, through which the negative sequence of the grid voltages is removed. This eliminates the estimation errors of conventional synchronous reference frame PLL and enhances its response speed with a higher bandwidth. The reforming process is supposed to be carried out at every zero-crossing point of the three-phase voltages and choose one phase as reference to balance the other two. Coefficients for the signal reforming are calculated at one zero-crossing point and updated until the next comes. In implementation, a certain phase is chosen as the reference all along and the reforming process will be suspended when it just crosses the zero line. This PLL algorithm has a fast and precise character to reform the three-phase grid voltages and is flexible for application. Under heavily distorted grid conditions, it can still perform effectively even with multiple zero-crossings. Comprehensive experimental results from a digital signal processor-based laboratory prototype are provided to validate the performance of this PLL algorithm.