TY - GEN
T1 - A radix-8 complex divider for FPGA implementation
AU - Wang, Dong
AU - Ercegovac, Miloš D.
AU - Zheng, Nanning
PY - 2009
Y1 - 2009
N2 - We present a design of a radix-8 complex division for fixed-point operands suitable for FPGA implementation. The design, consisting of operands' prescaling and digit recurrence, shares logic resources and optimizes the use of 6-input LUTs of FPGA devices for efficient design. An optimized single table for prescaling factors is developed. The design is implemented in Altera Stratix-II FPGA for several operands precisions and compared in cost, latency and power with a design using non-shared resources and with an IP-based design. The results show advantages of the proposed design in cost, delay, and power.
AB - We present a design of a radix-8 complex division for fixed-point operands suitable for FPGA implementation. The design, consisting of operands' prescaling and digit recurrence, shares logic resources and optimizes the use of 6-input LUTs of FPGA devices for efficient design. An optimized single table for prescaling factors is developed. The design is implemented in Altera Stratix-II FPGA for several operands precisions and compared in cost, latency and power with a design using non-shared resources and with an IP-based design. The results show advantages of the proposed design in cost, delay, and power.
UR - https://www.scopus.com/pages/publications/70449746459
U2 - 10.1109/FPL.2009.5272300
DO - 10.1109/FPL.2009.5272300
M3 - 会议稿件
AN - SCOPUS:70449746459
SN - 9781424438921
T3 - FPL 09: 19th International Conference on Field Programmable Logic and Applications
SP - 236
EP - 241
BT - FPL 09
T2 - FPL 09: 19th International Conference on Field Programmable Logic and Applications
Y2 - 31 August 2009 through 2 September 2009
ER -