TY - GEN
T1 - A New Dc-link Capacitor Voltage Balancing Method for Three-level SVM Strategies Based on Two-level Space Vector Diagram
AU - Woldegiorgis, Dereje
AU - Wei, Yuqi
AU - Mhiesan, Haider
AU - Mantooth, Alan
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/11/29
Y1 - 2020/11/29
N2 - This paper presents a new dc-link capacitor voltage balancing method for three-level Space Vector Modulation (SVM) strategies that are based on the space vector diagram of two-level inverters. The proposed method uses the time distribution of the local two-level zero vectors to achieve dc- link voltage balancing. It redistributes the zero vector times based on the magnitude and direction of the dc-link capacitor voltage deviations. The performance of the proposed capacitor voltage balancing method is compared with the conventional three-level SVM capacitor voltage balancing method that uses three-level redundant small vectors. The proposed method achieves significantly lower neutral-point voltage ripple compared to the conventional three-level SVM capacitor voltage balancing method for a wide range of modulation indices and load power factor values. Moreover, the code size and execution time are reduced by approximately 30 percent for use in microcontrollers.
AB - This paper presents a new dc-link capacitor voltage balancing method for three-level Space Vector Modulation (SVM) strategies that are based on the space vector diagram of two-level inverters. The proposed method uses the time distribution of the local two-level zero vectors to achieve dc- link voltage balancing. It redistributes the zero vector times based on the magnitude and direction of the dc-link capacitor voltage deviations. The performance of the proposed capacitor voltage balancing method is compared with the conventional three-level SVM capacitor voltage balancing method that uses three-level redundant small vectors. The proposed method achieves significantly lower neutral-point voltage ripple compared to the conventional three-level SVM capacitor voltage balancing method for a wide range of modulation indices and load power factor values. Moreover, the code size and execution time are reduced by approximately 30 percent for use in microcontrollers.
KW - Capacitor voltage Balance
KW - Digital Control
KW - Neutral-point voltage ripple
KW - Space Vector Modulation
KW - Three-level inverter
KW - common mode voltage
UR - https://www.scopus.com/pages/publications/85103152507
U2 - 10.1109/IPEMC-ECCEAsia48364.2020.9367733
DO - 10.1109/IPEMC-ECCEAsia48364.2020.9367733
M3 - 会议稿件
AN - SCOPUS:85103152507
T3 - 2020 IEEE 9th International Power Electronics and Motion Control Conference, IPEMC 2020 ECCE Asia
SP - 1746
EP - 1751
BT - 2020 IEEE 9th International Power Electronics and Motion Control Conference, IPEMC 2020 ECCE Asia
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 9th IEEE International Power Electronics and Motion Control Conference, IPEMC 2020 ECCE Asia
Y2 - 29 November 2020 through 2 December 2020
ER -