A list scheduling heuristic with new node priorities and critical child technique for task scheduling with communication contention

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6 Scopus citations

Abstract

Task scheduling is becoming an important aspect for parallel programming of modern embedded systems. In this chapter, the application to be scheduled is modeled as a Directed Acyclic Graph (DAG), and the architecture targets parallel embedded systems composed of multiple processors interconnected by buses and/or switches. This chapter presents new list scheduling heuristics with communication contention. Furthermore, we define new node priorities (top level and bottom level) to sort nodes, and propose an advanced technique named critical child to select a processor to execute a node. Experimental results show that the proposed method is effective to reduce the schedule length, and the runtime performance is greatly improved in the cases of medium and high communication. Since the communication cost is increasing from medium to high in modern applications like digital communication and video compression, the proposed method is well-adapted for scheduling these applications over parallel embedded systems.

Original languageEnglish
Title of host publicationAlgorithm-Architecture Matching for Signal and Image Processing - Best Papers from Design and Architectures for Signal and Image Processing 2007 and 2008 and 2009
EditorsGuy Gogniat, Dragomir Milojevic, Adam Morawiec, Ahmet Erdogan
Pages217-236
Number of pages20
DOIs
StatePublished - 2011

Publication series

NameLecture Notes in Electrical Engineering
Volume73 LNEE
ISSN (Print)1876-1100
ISSN (Electronic)1876-1119

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