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A highly linear low power envelope detector

  • Yi Bo Su
  • , Qin Xia
  • , Li Geng
  • , Xin Ke Liu
  • Xi'an Jiaotong University
  • Shenzhen University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper presents a direct voltage detection architecture that can be used for linear envelope detectors. A preamplifier using a common-gate (CG) common-source (CS) circuit topology sends the input modulated signal to a differential output and is coupled to a pair of common source stages. By using the quadratic IV curve of the MOSFETs, the detector can achieve linear operations on the detected envelope signals. The envelope detector was designed using a standard 0.18 \mu n CMOS process. The simulation result shows the detector can track a 120 MHz modulation signal at cost of 18 mW of static power with a 1.8 V power supply.

Original languageEnglish
Title of host publication2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728102863
DOIs
StatePublished - Jun 2019
Event2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019 - Xi'an, China
Duration: 12 Jun 201914 Jun 2019

Publication series

Name2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019

Conference

Conference2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019
Country/TerritoryChina
CityXi'an
Period12/06/1914/06/19

Keywords

  • Linear envelope detector
  • Low power
  • Wideband

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