A high-throughput fixed-point complex divider for FPGAs

This paper presents a high-throughput fixed-point complex divider which uses four pipelined CORDIC units to transform and divide complex numbers in Polar coordinates. By persevering the macro-angle for CORDIC rotations in redundant form and developing an optimized pipelining structure, the FPGA based implementation achieves a 9× advantage on throughput over the best design reported. In addition, the final error is guaranteed within 1 ulp (unit in last position). Thus the proposed complex divider is highly suitable for accelerating DSP applications with high precision numerical accuracy requirements.