A High-Speed PET Readout Analog Front End Circuit Based on the Split-Integration Algorithm

This paper presents a novel charge measurement approach and, based on this, designs a high speed and high precision analog front end (AFE) circuit for positron emission tomography systems. The proposed split-integration algorithm (SIA) achieves good linearity with only simple processing of the data output by the AFE, eliminating the need for complex nonlinear calibration. A trans-impedance amplifier (TIA) is used for the preamplifier to meet the requirements of low input impedance, low noise, and high-speed applications. The proposed peak detection and hold (PDH) circuit structure overcomes the issue of deteriorated measurement accuracy in high-speed applications. The novel readout method enhances the readout efficiency of the AFE. The chip is implemented in a 55 nm CMOS process, occupying an area of 0.525 mm². Postlayout simulation results indicate that with a detector capacitance of 10 pF, the low noise amplifier (LNA) achieves a gain of 99.4 dB, a bandwidth of 103.5 MHz, and an equivalent input noise current of 4.16 pA/√Hz. Under the condition of an input voltage peak arrival time of 10 ns, the maximum relative error voltage of the PDH circuit is only 1.467%. Each readout channel dissipates 10.8 mW of power, and a non-linearity error of 2.14% can be achieved with a shaping time of 10 ns.