TY - GEN
T1 - A high performance and low cost video processing SoC for digital HDTV systems
AU - Liu, Longjun
AU - Sun, Hongbin
AU - Zhao, Wenzhe
AU - Hou, Zuoxun
AU - Xin, Jingmin
AU - Zheng, Nanning
PY - 2011
Y1 - 2011
N2 - This paper proposes a video processing SoC for Flat Panel Displays and describes the employed video processing algorithms. Three key techniques integrated in the proposed chip are introduced, including spatio-temporal adaptive TV decoder, square-nonlinear interpolation scaler and efficient memory controller. The overall video processing architecture is fabricated at 0.18um CMOS technology node, and the IC is extensively evaluated in a prototype HDTV Set. The proposed SoC chip can well supports both SDTV and HDTV signals, while providing high quality images.
AB - This paper proposes a video processing SoC for Flat Panel Displays and describes the employed video processing algorithms. Three key techniques integrated in the proposed chip are introduced, including spatio-temporal adaptive TV decoder, square-nonlinear interpolation scaler and efficient memory controller. The overall video processing architecture is fabricated at 0.18um CMOS technology node, and the IC is extensively evaluated in a prototype HDTV Set. The proposed SoC chip can well supports both SDTV and HDTV signals, while providing high quality images.
UR - https://www.scopus.com/pages/publications/84860845399
U2 - 10.1109/ASICON.2011.6157153
DO - 10.1109/ASICON.2011.6157153
M3 - 会议稿件
AN - SCOPUS:84860845399
SN - 9781612841908
T3 - Proceedings of International Conference on ASIC
SP - 188
EP - 191
BT - Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
T2 - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
Y2 - 25 October 2011 through 28 October 2011
ER -