TY - GEN
T1 - A high efficient hardware architecture for multiview 3DTV
AU - Yu, Jiang
AU - Liu, Geng
AU - Zhang, Xin
AU - Ren, Pengju
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/3/11
Y1 - 2015/3/11
N2 - There are three main challenges to design an efficient multiview 3DTV SoC:(1)how to organize DRAM address mapping to maximize off-chip bandwidth utilization;(2)how to design a parallel configurable image scaling engine to interpolate various viewpoints in real-time; (3)how to reduce computational complexity of float-point sub-pixel rearrangement with sufficient accuracy. To this end, we present a highly optimized hardware architecture, which saves 38.4% logic and 37.5% memory resources when implementing a multiview 1080P@60Hz 3DTV on the Xilinx XC5VLX330 FPGA.
AB - There are three main challenges to design an efficient multiview 3DTV SoC:(1)how to organize DRAM address mapping to maximize off-chip bandwidth utilization;(2)how to design a parallel configurable image scaling engine to interpolate various viewpoints in real-time; (3)how to reduce computational complexity of float-point sub-pixel rearrangement with sufficient accuracy. To this end, we present a highly optimized hardware architecture, which saves 38.4% logic and 37.5% memory resources when implementing a multiview 1080P@60Hz 3DTV on the Xilinx XC5VLX330 FPGA.
UR - https://www.scopus.com/pages/publications/84926465829
U2 - 10.1109/ASPDAC.2015.7058927
DO - 10.1109/ASPDAC.2015.7058927
M3 - 会议稿件
AN - SCOPUS:84926465829
T3 - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
SP - 22
EP - 23
BT - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Y2 - 19 January 2015 through 22 January 2015
ER -