TY - GEN
T1 - A heterogeneous design methodology for STT-RAM memory system of mobile SoC
AU - Lv, Minjie
AU - Sun, Hongbin
AU - Min, Tai
AU - Zhang, Tong
AU - Zheng, Nanning
PY - 2012
Y1 - 2012
N2 - Spin-torque transfer random access memory (STT-RAM) has emerged as a potential candidate for universal memory. To exploit its use in System-on-Chip (SoC), this paper proposes a heterogeneous design methodology, which leverages different circuit and structure design techniques to significantly improve the overall efficiency of STT-RAM based memory system, without incurring any extra technology process cost. By using Cacti 6.5 and SimpleScalar simulator, we further demonstrate the performance and efficiency benefit of proposed design methodology in a mobile SoC.
AB - Spin-torque transfer random access memory (STT-RAM) has emerged as a potential candidate for universal memory. To exploit its use in System-on-Chip (SoC), this paper proposes a heterogeneous design methodology, which leverages different circuit and structure design techniques to significantly improve the overall efficiency of STT-RAM based memory system, without incurring any extra technology process cost. By using Cacti 6.5 and SimpleScalar simulator, we further demonstrate the performance and efficiency benefit of proposed design methodology in a mobile SoC.
UR - https://www.scopus.com/pages/publications/84874916545
U2 - 10.1109/ICSICT.2012.6467751
DO - 10.1109/ICSICT.2012.6467751
M3 - 会议稿件
AN - SCOPUS:84874916545
SN - 9781467324724
T3 - ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
BT - ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
T2 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012
Y2 - 29 October 2012 through 1 November 2012
ER -