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A dual-path open-loop CMOS slew-rate controlled output driver with low PVT variation

  • Xiaoyan Gui
  • , Kai Li
  • , Xiaoli Wang
  • , Li Geng
  • Xi'an Jiaotong University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

A dual-path open-loop slew-rate controlled CMOS driver is presented. The proposed output driver incorporates a delay-locked loop (DLL) to minimize the slew-rate variation over process, voltage and temperature (PVT). A dual-path open-loop structure is introduced to cancel the high-frequency components of the output signal. Simulation using the Global Foundry 0.18µm CMOS process shows that the driver achieves less than 0.66V/ns slew-rate variation operating at 500 Mbps over 16 corners, corresponding to 56% reduction compared with that of a conventional output driver.

Original languageEnglish
Title of host publication2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages274-277
Number of pages4
ISBN (Electronic)9781538673928
DOIs
StatePublished - 2 Jul 2018
Event61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 - Windsor, Canada
Duration: 5 Aug 20188 Aug 2018

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2018-August
ISSN (Print)1548-3746

Conference

Conference61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018
Country/TerritoryCanada
CityWindsor
Period5/08/188/08/18

Keywords

  • DLL
  • EM radiation
  • Output driver
  • Slew rate control

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