TY - GEN
T1 - A Digital Sensor-less Synchronous Rectification Algorithm for Symmetrical Bidirectional CLLC Resonant Converters
AU - Ren, Xufu
AU - Pei, Long
AU - Song, Shaojie
AU - Zhang, Jialei
AU - Pei, Yunqing
AU - Wang, Laili
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/3
Y1 - 2020/3
N2 - For bidirectional CLLC resonant converters, synchronous rectification (SR) is a key technique that can reduce the conduction losses by replacing the diodes to bring an improvement of the performance. Unfortunately, existing methods suffer from high cost, complex hardware and imprecise control effect. Aiming at these problems, this paper proposes a digital sensor-less SR algorithm based on time domain model for symmetrical CLLC converters under pulse frequency modulation (PFM). The developed approach can enable the SR switching action more precisely within almost full load range without any additional hardware, e.g., anti-parallel diode, SR IC and high bandwidth sensor. Its implementation only needs to measure the DC signal (i.e., the output current), rather than to sense the zero-crossing point of the high frequency resonant current. Additionally, a simplification of the algorithm has been made with no accuracy compromise, thus the requirements of the digital controller decrease greatly. Finally, experiments have been performed on a prototype to verify the validity and applicability of the presented SR algorithm, and the experimental results show that the SR effects are substantially improved.
AB - For bidirectional CLLC resonant converters, synchronous rectification (SR) is a key technique that can reduce the conduction losses by replacing the diodes to bring an improvement of the performance. Unfortunately, existing methods suffer from high cost, complex hardware and imprecise control effect. Aiming at these problems, this paper proposes a digital sensor-less SR algorithm based on time domain model for symmetrical CLLC converters under pulse frequency modulation (PFM). The developed approach can enable the SR switching action more precisely within almost full load range without any additional hardware, e.g., anti-parallel diode, SR IC and high bandwidth sensor. Its implementation only needs to measure the DC signal (i.e., the output current), rather than to sense the zero-crossing point of the high frequency resonant current. Additionally, a simplification of the algorithm has been made with no accuracy compromise, thus the requirements of the digital controller decrease greatly. Finally, experiments have been performed on a prototype to verify the validity and applicability of the presented SR algorithm, and the experimental results show that the SR effects are substantially improved.
KW - CLLC
KW - resonant converter
KW - synchronous rectification
KW - time domain model
UR - https://www.scopus.com/pages/publications/85087741394
U2 - 10.1109/APEC39645.2020.9124171
DO - 10.1109/APEC39645.2020.9124171
M3 - 会议稿件
AN - SCOPUS:85087741394
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 962
EP - 968
BT - APEC 2020 - 35th Annual IEEE Applied Power Electronics Conference and Exposition
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2020
Y2 - 15 March 2020 through 19 March 2020
ER -