TY - GEN
T1 - A CMOS Low-Noise Fast-Settling BM-TIA with CM-Post-Amplifier Chip Connectivity for 50G-PON
AU - Xia, Yifei
AU - Zhang, Zhixing
AU - Ma, Shuaizhe
AU - Yao, Yuanhao
AU - Yang, Ruixuan
AU - Yang, Yuye
AU - Yang, Jianyu
AU - Geng, Li
AU - Li, Dan
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - With the bandwidth demand keeps growing, the next generation 50Gb/s Passive Optical Network (PON) is on the horizon. As the high-speed access network for most users, the increase in the cost of devices and modules makes low-cost components more desirable. Meanwhile, the multi-Km transmission distance and several layers of lossy optical splitter in PON dictate more sensitive receiver than those used in the datacenter. In the optical line termination (OLT) side, high-speed burst-mode (BM) transimpedance amplifiers (TIA) are mostly made by SiGe BiCMOS [1]-[3] to realize the harsh noise and settling time targets, with higher cost and large power consumption. Targeting on datacenter applications, some recent CMOS TIAs [4]-[5] have accomplished rapid BM settling through mixed-signal techniques. However, they can't be easily applied to BM-TIA for PON in the absence of clocking. Moreover, the post-amplifier chip that follows the BM-TIA needs also to be burst-mode amplifier, further complicating the system design with deteriorated performance and cost. In this paper, we address the noise and settling time challenges in the design of a 50-Gb/s CMOS BM-TIA for low cost, which also highlights its unique capability to drive a continuous-mode (CM) post-amplifier chip in BM application.
AB - With the bandwidth demand keeps growing, the next generation 50Gb/s Passive Optical Network (PON) is on the horizon. As the high-speed access network for most users, the increase in the cost of devices and modules makes low-cost components more desirable. Meanwhile, the multi-Km transmission distance and several layers of lossy optical splitter in PON dictate more sensitive receiver than those used in the datacenter. In the optical line termination (OLT) side, high-speed burst-mode (BM) transimpedance amplifiers (TIA) are mostly made by SiGe BiCMOS [1]-[3] to realize the harsh noise and settling time targets, with higher cost and large power consumption. Targeting on datacenter applications, some recent CMOS TIAs [4]-[5] have accomplished rapid BM settling through mixed-signal techniques. However, they can't be easily applied to BM-TIA for PON in the absence of clocking. Moreover, the post-amplifier chip that follows the BM-TIA needs also to be burst-mode amplifier, further complicating the system design with deteriorated performance and cost. In this paper, we address the noise and settling time challenges in the design of a 50-Gb/s CMOS BM-TIA for low cost, which also highlights its unique capability to drive a continuous-mode (CM) post-amplifier chip in BM application.
UR - https://www.scopus.com/pages/publications/105007016370
U2 - 10.1109/CICC63670.2025.10982699
DO - 10.1109/CICC63670.2025.10982699
M3 - 会议稿件
AN - SCOPUS:105007016370
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - 2025 IEEE Custom Integrated Circuits Conference, CICC 2025 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 45th Annual IEEE Custom Integrated Circuits Conference, CICC 2025
Y2 - 13 April 2025 through 17 April 2025
ER -