A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure

Yan Song; Yan Zhu; Chi Hang Chan; Li Geng; Rui Paulo Martins

doi:10.1109/VLSIC.2018.8502382

A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure

Yan Song
, Yan Zhu
, Chi Hang Chan
, Li Geng
, Rui Paulo Martins

Faculty of Electronic and Information Engineering

University of Macau
Xi'an Jiaotong University
University of Lisbon

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

24 Scopus citations

Abstract

This paper presents a wide-band and energy-efficient 0-1 MASH ΣΔ ADC which is realized based on the pipelined-SAR structure. Composed by a 6b SAR ADC in the 1^st-stage and a 5b SAR ADC in the 2^nd-stage, with alternate loading capacitors (ALC) reused for error feedback, it realizes an ideal 1^st-order noise shaping while simultaneously maintaining a high-speed pipeline operation. Fabricated in 65nm CMOS, the prototype consumes 4.5mW from a 1.2V supply with 77dB SNDR over 12.5MHz bandwidth, leading to a 171.5dB Schreier FoM.

Original language	English
Title of host publication	2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	203-204
Number of pages	2
ISBN (Electronic)	9781538667002
DOIs	https://doi.org/10.1109/VLSIC.2018.8502382
State	Published - 22 Oct 2018
Event	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States Duration: 18 Jun 2018 → 22 Jun 2018

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2018-June

Conference

Conference	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Country/Territory	United States
City	Honolulu
Period	18/06/18 → 22/06/18

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10.1109/VLSIC.2018.8502382

Cite this

Song, Y., Zhu, Y., Chan, C. H., Geng, L., & Martins, R. P. (2018). A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 (pp. 203-204). Article 8502382 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2018.8502382

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title = "A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure",

abstract = "This paper presents a wide-band and energy-efficient 0-1 MASH ΣΔ ADC which is realized based on the pipelined-SAR structure. Composed by a 6b SAR ADC in the 1st-stage and a 5b SAR ADC in the 2nd-stage, with alternate loading capacitors (ALC) reused for error feedback, it realizes an ideal 1st-order noise shaping while simultaneously maintaining a high-speed pipeline operation. Fabricated in 65nm CMOS, the prototype consumes 4.5mW from a 1.2V supply with 77dB SNDR over 12.5MHz bandwidth, leading to a 171.5dB Schreier FoM.",

author = "Yan Song and Yan Zhu and Chan, \{Chi Hang\} and Li Geng and Martins, \{Rui Paulo\}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 ; Conference date: 18-06-2018 Through 22-06-2018",

year = "2018",

month = oct,

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doi = "10.1109/VLSIC.2018.8502382",

language = "英语",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

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Song, Y, Zhu, Y, Chan, CH, Geng, L & Martins, RP 2018, A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure. in 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018., 8502382, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 203-204, 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018, Honolulu, United States, 18/06/18. https://doi.org/10.1109/VLSIC.2018.8502382

A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure. / Song, Yan; Zhu, Yan; Chan, Chi Hang et al.
2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 203-204 8502382 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents a wide-band and energy-efficient 0-1 MASH ΣΔ ADC which is realized based on the pipelined-SAR structure. Composed by a 6b SAR ADC in the 1st-stage and a 5b SAR ADC in the 2nd-stage, with alternate loading capacitors (ALC) reused for error feedback, it realizes an ideal 1st-order noise shaping while simultaneously maintaining a high-speed pipeline operation. Fabricated in 65nm CMOS, the prototype consumes 4.5mW from a 1.2V supply with 77dB SNDR over 12.5MHz bandwidth, leading to a 171.5dB Schreier FoM.

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A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure

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