A 54-68 GHz Power Amplifier with Improved Linearity and Efficiency in 40 nm CMOS

Hamed Mosalam; Wenbo Xiao; Xiaoyan Gui; Dan Li; Quan Pan

doi:10.1109/TCSII.2021.3084628

A 54-68 GHz Power Amplifier with Improved Linearity and Efficiency in 40 nm CMOS

Hamed Mosalam
, Wenbo Xiao
, Xiaoyan Gui
, Dan Li
, Quan Pan

Faculty of Electronic and Information Engineering

Research output: Contribution to journal › Article › peer-review

15 Scopus citations

Abstract

This brief presents a 54-68 GHz two-stage power amplifier (PA) with linearity and efficiency enhancement in a 40 nm CMOS process. The first stage adopts a current reuse cascaded common-source (CS) structure with a shunt RC feedback to maximize the gain and minimize the DC power consumption to boost the linearity and efficiency, while the second stage is a cascode structure with two built-in linearizers to enhance the linearity much further. Based on the proposed structure, the fabricated PA exhibits measured output of 1-dB compression point, saturated output power, power added efficiency (PAE) and AM-PM distortion of +14 dBm, +15 dBm, 20% and 8 degrees, respectively. In addition, the proposed CMOS PA achieves high and flat power gain of 14 dB with ripple less than 1.5 dB through the operating 54 - 68 GHz frequency band while consuming only 110 mW.

Original language	English
Pages (from-to)	40-44
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	69
Issue number	1
DOIs	https://doi.org/10.1109/TCSII.2021.3084628
State	Published - 1 Jan 2022

Keywords

1-dB compression
60 GHz
CMOS
Millimeter-wave
PAE
power amplifier (PA)

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10.1109/TCSII.2021.3084628

Cite this

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title = "A 54-68 GHz Power Amplifier with Improved Linearity and Efficiency in 40 nm CMOS",

abstract = "This brief presents a 54-68 GHz two-stage power amplifier (PA) with linearity and efficiency enhancement in a 40 nm CMOS process. The first stage adopts a current reuse cascaded common-source (CS) structure with a shunt RC feedback to maximize the gain and minimize the DC power consumption to boost the linearity and efficiency, while the second stage is a cascode structure with two built-in linearizers to enhance the linearity much further. Based on the proposed structure, the fabricated PA exhibits measured output of 1-dB compression point, saturated output power, power added efficiency (PAE) and AM-PM distortion of +14 dBm, +15 dBm, 20\% and 8 degrees, respectively. In addition, the proposed CMOS PA achieves high and flat power gain of 14 dB with ripple less than 1.5 dB through the operating 54 - 68 GHz frequency band while consuming only 110 mW.",

keywords = "1-dB compression, 60 GHz, CMOS, Millimeter-wave, PAE, power amplifier (PA)",

author = "Hamed Mosalam and Wenbo Xiao and Xiaoyan Gui and Dan Li and Quan Pan",

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AU - Mosalam, Hamed

AU - Xiao, Wenbo

AU - Gui, Xiaoyan

AU - Li, Dan

AU - Pan, Quan

PY - 2022/1/1

Y1 - 2022/1/1

N2 - This brief presents a 54-68 GHz two-stage power amplifier (PA) with linearity and efficiency enhancement in a 40 nm CMOS process. The first stage adopts a current reuse cascaded common-source (CS) structure with a shunt RC feedback to maximize the gain and minimize the DC power consumption to boost the linearity and efficiency, while the second stage is a cascode structure with two built-in linearizers to enhance the linearity much further. Based on the proposed structure, the fabricated PA exhibits measured output of 1-dB compression point, saturated output power, power added efficiency (PAE) and AM-PM distortion of +14 dBm, +15 dBm, 20% and 8 degrees, respectively. In addition, the proposed CMOS PA achieves high and flat power gain of 14 dB with ripple less than 1.5 dB through the operating 54 - 68 GHz frequency band while consuming only 110 mW.

AB - This brief presents a 54-68 GHz two-stage power amplifier (PA) with linearity and efficiency enhancement in a 40 nm CMOS process. The first stage adopts a current reuse cascaded common-source (CS) structure with a shunt RC feedback to maximize the gain and minimize the DC power consumption to boost the linearity and efficiency, while the second stage is a cascode structure with two built-in linearizers to enhance the linearity much further. Based on the proposed structure, the fabricated PA exhibits measured output of 1-dB compression point, saturated output power, power added efficiency (PAE) and AM-PM distortion of +14 dBm, +15 dBm, 20% and 8 degrees, respectively. In addition, the proposed CMOS PA achieves high and flat power gain of 14 dB with ripple less than 1.5 dB through the operating 54 - 68 GHz frequency band while consuming only 110 mW.

KW - 1-dB compression

KW - 60 GHz

KW - CMOS

KW - Millimeter-wave

KW - PAE

KW - power amplifier (PA)

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VL - 69

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JO - IEEE Transactions on Circuits and Systems II: Express Briefs

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ER -

A 54-68 GHz Power Amplifier with Improved Linearity and Efficiency in 40 nm CMOS

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Keywords

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