A 3D MCAM architecture based on flash memory enabling binary neural network computing for edge AI

The in-memory computing (IMC) architecture implemented by non-volatile memory units shows great possibilities to break the traditional von Neumann bottleneck. In this paper, a 3D IMC architecture is proposed whose unit is based on a multi-bit content-addressable memory (MCAM). The MCAM unit is comprised of two 65 nm flash memory and two transistors (2Flash2T), which is reconfigurable and multifunctional for both data write/search and XNOR logic operation. Moreover, the MCAM array can also support the population count (POPCOUNT) operation, which can be beneficial for the training and inference process in binary neural network (BNN) computing. Based on the well-known MNIST dataset, the proposed 3D MCAM architecture shows a 98.63% recognition accuracy and a 300% noise-tolerant performance without significant accuracy deterioration. Our findings can provide the potential for developing highly energy-efficient BNN computing for complex artificial intelligence (AI) tasks based on flash-based MCAM units.