A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4

Dan Li; Gabriele Minoia; Matteo Repossi; Daniele Baldi; Enrico Temporiti; Andrea Mazzanti; Francesco Svelto

doi:10.1109/ESSCIRC.2012.6341298

A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4

Dan Li
, Gabriele Minoia
, Matteo Repossi
, Daniele Baldi
, Enrico Temporiti
, Andrea Mazzanti
, Francesco Svelto

University of Pavia
STMicroelectronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

Shunt-feedback TIAs suffer from a trade-off between noise and bandwidth. In this work we propose a two stage 25Gb/s front-end, made of a low noise narrow-band TIA followed by an equalizer aimed at restoring the required bandwidth, providing a 4x noise power reduction compared to a traditional design approach. A 65nm receiver cascading the proposed front-end, the limiting amplifier and a buffer, tailored to 100GBASE-LR4, demonstrates a gain of 83dBΩ, an input referred equivalent rms noise current of 2.44μA and an electrical analog bandwidth tunable between 10.6GHz and 18.2GHz. The power consumption is 93mW with a FOM of 2066GHz·Ω/mW.

Original language	English
Title of host publication	2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012
Pages	221-224
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2012.6341298
State	Published - 2012
Externally published	Yes
Event	38th European Solid State Circuits Conference, ESSCIRC 2012 - Bordeaux, France Duration: 17 Sep 2012 → 21 Sep 2012

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	38th European Solid State Circuits Conference, ESSCIRC 2012
Country/Territory	France
City	Bordeaux
Period	17/09/12 → 21/09/12

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10.1109/ESSCIRC.2012.6341298

Cite this

@inproceedings{b9875abe837f406389901d715686043a,

title = "A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4",

abstract = "Shunt-feedback TIAs suffer from a trade-off between noise and bandwidth. In this work we propose a two stage 25Gb/s front-end, made of a low noise narrow-band TIA followed by an equalizer aimed at restoring the required bandwidth, providing a 4x noise power reduction compared to a traditional design approach. A 65nm receiver cascading the proposed front-end, the limiting amplifier and a buffer, tailored to 100GBASE-LR4, demonstrates a gain of 83dBΩ, an input referred equivalent rms noise current of 2.44μA and an electrical analog bandwidth tunable between 10.6GHz and 18.2GHz. The power consumption is 93mW with a FOM of 2066GHz·Ω/mW.",

author = "Dan Li and Gabriele Minoia and Matteo Repossi and Daniele Baldi and Enrico Temporiti and Andrea Mazzanti and Francesco Svelto",

year = "2012",

doi = "10.1109/ESSCIRC.2012.6341298",

language = "英语",

isbn = "9781467322126",

series = "European Solid-State Circuits Conference",

pages = "221--224",

booktitle = "2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012",

note = "38th European Solid State Circuits Conference, ESSCIRC 2012 ; Conference date: 17-09-2012 Through 21-09-2012",

}

Li, D, Minoia, G, Repossi, M, Baldi, D, Temporiti, E, Mazzanti, A & Svelto, F 2012, A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4. in 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012., 6341298, European Solid-State Circuits Conference, pp. 221-224, 38th European Solid State Circuits Conference, ESSCIRC 2012, Bordeaux, France, 17/09/12. https://doi.org/10.1109/ESSCIRC.2012.6341298

TY - GEN

T1 - A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4

AU - Li, Dan

AU - Minoia, Gabriele

AU - Repossi, Matteo

AU - Baldi, Daniele

AU - Temporiti, Enrico

AU - Mazzanti, Andrea

AU - Svelto, Francesco

PY - 2012

Y1 - 2012

N2 - Shunt-feedback TIAs suffer from a trade-off between noise and bandwidth. In this work we propose a two stage 25Gb/s front-end, made of a low noise narrow-band TIA followed by an equalizer aimed at restoring the required bandwidth, providing a 4x noise power reduction compared to a traditional design approach. A 65nm receiver cascading the proposed front-end, the limiting amplifier and a buffer, tailored to 100GBASE-LR4, demonstrates a gain of 83dBΩ, an input referred equivalent rms noise current of 2.44μA and an electrical analog bandwidth tunable between 10.6GHz and 18.2GHz. The power consumption is 93mW with a FOM of 2066GHz·Ω/mW.

AB - Shunt-feedback TIAs suffer from a trade-off between noise and bandwidth. In this work we propose a two stage 25Gb/s front-end, made of a low noise narrow-band TIA followed by an equalizer aimed at restoring the required bandwidth, providing a 4x noise power reduction compared to a traditional design approach. A 65nm receiver cascading the proposed front-end, the limiting amplifier and a buffer, tailored to 100GBASE-LR4, demonstrates a gain of 83dBΩ, an input referred equivalent rms noise current of 2.44μA and an electrical analog bandwidth tunable between 10.6GHz and 18.2GHz. The power consumption is 93mW with a FOM of 2066GHz·Ω/mW.

UR - https://www.scopus.com/pages/publications/84870782294

U2 - 10.1109/ESSCIRC.2012.6341298

DO - 10.1109/ESSCIRC.2012.6341298

M3 - 会议稿件

AN - SCOPUS:84870782294

SN - 9781467322126

T3 - European Solid-State Circuits Conference

SP - 221

EP - 224

BT - 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012

T2 - 38th European Solid State Circuits Conference, ESSCIRC 2012

Y2 - 17 September 2012 through 21 September 2012

ER -

A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4

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