A 200-Gb/s Low-Noise TIA in 28-nm CMOS

Feiyang Zhang; Jianyu Yang; Yifei Xia; Zhixing Zhang; Ruixuan Yang; Liang Zhao; Wenxin Zhang; Cailing Li; Zetong Zhang; Shenlei Bao; Binhao Wang; Li Geng; Dan Li

doi:10.1109/RFIC70222.2026.11602369

A 200-Gb/s Low-Noise TIA in 28-nm CMOS

Feiyang Zhang
, Jianyu Yang
, Yifei Xia
, Zhixing Zhang
, Ruixuan Yang
, Liang Zhao
, Wenxin Zhang
, Cailing Li
, Zetong Zhang
, Shenlei Bao
, Binhao Wang
, Li Geng
, Dan Li

Faculty of Electronic and Information Engineering

Xi'an Jiaotong University
CAS - Xi'an Institute of Optics and Precision Mechanics
University of Chinese Academy of Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a 200-Gb/s low-noise transimpedance amplifier (TIA) implemented in standard 28-nm CMOS technology, addressing the escalating bandwidth demands of artificial intelligence data centers (AIDCs). The proposed TIA employs a three-stage front-end with a inductive peaking strategy, a single-to-differential equalizer (S2D-EQ), and a linear CML output buffer for signal performance. The TIA achieves transimpedance gain of 61.6 dBΩ, an O-E bandwidth of 48 GHz, and an input-referred noise density of 11.5 pA/√Hz while consuming 116 mW (0.58 pJ/bit). The TIA supports 100-GBaud PAM-4 modulation, validating its suitability for nextgeneration high-density optical communication systems.

Original language	English
Title of host publication	2026 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2026
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	315-318
Number of pages	4
ISBN (Electronic)	9798319518033
DOIs	https://doi.org/10.1109/RFIC70222.2026.11602369
State	Published - 2026
Event	2026 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2026 - Boston, United States Duration: 7 Jun 2026 → 9 Jun 2026

Publication series

Name	Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)	1529-2517

Conference

Conference	2026 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2026
Country/Territory	United States
City	Boston
Period	7/06/26 → 9/06/26

Keywords

CMOS
inductive peaking
low noise
power efficiency
Trans-impedance Amplifier (TIA)

Access to Document

10.1109/RFIC70222.2026.11602369

Cite this

Zhang, F., Yang, J., Xia, Y., Zhang, Z., Yang, R., Zhao, L., Zhang, W., Li, C., Zhang, Z., Bao, S., Wang, B., Geng, L., & Li, D. (2026). A 200-Gb/s Low-Noise TIA in 28-nm CMOS. In 2026 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2026 (pp. 315-318). (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RFIC70222.2026.11602369

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title = "A 200-Gb/s Low-Noise TIA in 28-nm CMOS",

abstract = "This paper presents a 200-Gb/s low-noise transimpedance amplifier (TIA) implemented in standard 28-nm CMOS technology, addressing the escalating bandwidth demands of artificial intelligence data centers (AIDCs). The proposed TIA employs a three-stage front-end with a inductive peaking strategy, a single-to-differential equalizer (S2D-EQ), and a linear CML output buffer for signal performance. The TIA achieves transimpedance gain of 61.6 dBΩ, an O-E bandwidth of 48 GHz, and an input-referred noise density of 11.5 pA/√Hz while consuming 116 mW (0.58 pJ/bit). The TIA supports 100-GBaud PAM-4 modulation, validating its suitability for nextgeneration high-density optical communication systems.",

keywords = "CMOS, inductive peaking, low noise, power efficiency, Trans-impedance Amplifier (TIA)",

author = "Feiyang Zhang and Jianyu Yang and Yifei Xia and Zhixing Zhang and Ruixuan Yang and Liang Zhao and Wenxin Zhang and Cailing Li and Zetong Zhang and Shenlei Bao and Binhao Wang and Li Geng and Dan Li",

note = "Publisher Copyright: {\textcopyright} 2026 IEEE.; 2026 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2026 ; Conference date: 07-06-2026 Through 09-06-2026",

year = "2026",

doi = "10.1109/RFIC70222.2026.11602369",

language = "英语",

series = "Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "315--318",

booktitle = "2026 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2026",

}

Zhang, F, Yang, J, Xia, Y, Zhang, Z, Yang, R, Zhao, L, Zhang, W, Li, C, Zhang, Z, Bao, S, Wang, B, Geng, L & Li, D 2026, A 200-Gb/s Low-Noise TIA in 28-nm CMOS. in 2026 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2026. Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, Institute of Electrical and Electronics Engineers Inc., pp. 315-318, 2026 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2026, Boston, United States, 7/06/26. https://doi.org/10.1109/RFIC70222.2026.11602369

A 200-Gb/s Low-Noise TIA in 28-nm CMOS. / Zhang, Feiyang; Yang, Jianyu; Xia, Yifei et al.
2026 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2026. Institute of Electrical and Electronics Engineers Inc., 2026. p. 315-318 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 200-Gb/s Low-Noise TIA in 28-nm CMOS

AU - Zhang, Feiyang

AU - Yang, Jianyu

AU - Xia, Yifei

AU - Zhang, Zhixing

AU - Yang, Ruixuan

AU - Zhao, Liang

AU - Zhang, Wenxin

AU - Li, Cailing

AU - Zhang, Zetong

AU - Bao, Shenlei

AU - Wang, Binhao

AU - Geng, Li

AU - Li, Dan

PY - 2026

Y1 - 2026

N2 - This paper presents a 200-Gb/s low-noise transimpedance amplifier (TIA) implemented in standard 28-nm CMOS technology, addressing the escalating bandwidth demands of artificial intelligence data centers (AIDCs). The proposed TIA employs a three-stage front-end with a inductive peaking strategy, a single-to-differential equalizer (S2D-EQ), and a linear CML output buffer for signal performance. The TIA achieves transimpedance gain of 61.6 dBΩ, an O-E bandwidth of 48 GHz, and an input-referred noise density of 11.5 pA/√Hz while consuming 116 mW (0.58 pJ/bit). The TIA supports 100-GBaud PAM-4 modulation, validating its suitability for nextgeneration high-density optical communication systems.

AB - This paper presents a 200-Gb/s low-noise transimpedance amplifier (TIA) implemented in standard 28-nm CMOS technology, addressing the escalating bandwidth demands of artificial intelligence data centers (AIDCs). The proposed TIA employs a three-stage front-end with a inductive peaking strategy, a single-to-differential equalizer (S2D-EQ), and a linear CML output buffer for signal performance. The TIA achieves transimpedance gain of 61.6 dBΩ, an O-E bandwidth of 48 GHz, and an input-referred noise density of 11.5 pA/√Hz while consuming 116 mW (0.58 pJ/bit). The TIA supports 100-GBaud PAM-4 modulation, validating its suitability for nextgeneration high-density optical communication systems.

KW - CMOS

KW - inductive peaking

KW - low noise

KW - power efficiency

KW - Trans-impedance Amplifier (TIA)

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T3 - Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

SP - 315

EP - 318

BT - 2026 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2026

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2026 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2026

Y2 - 7 June 2026 through 9 June 2026

ER -

A 200-Gb/s Low-Noise TIA in 28-nm CMOS

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