A 1.5MSPS, 120 dB SFDR, ±10 V input range SAR ADC with sampling nonlinearity compensation and inherent 2-b coarse ADC for MSBs decision

This paper presents a high-precision, successive-approximation-register (SAR) analog-to-digital converter (ADC) with maximum input range of ±10 V for industry applications, where the wide-range input signal is sampled directly on part of the capacitive digital-to-analog converter (CDAC) via high-voltage (HV) sampling switches. An inherent 2-b coarse ADC is designed to avoid charge leakage under large input signal, which is reused for nonlinearity compensation from the sampling switch's resistance, while the nonlinearity due to clock feedthrough is compensated by a binary capacitor array. A capacitance reduction structure is used in the CDAC with redundant bits to save the CDAC's area. Fabricated in a 180-nm CMOS process with HV option, the ADC achieves 102-dB SNDR and 120-dB SFDR under 1.5 MSPS throughput. The overall power consumption without BGR and reference buffer is 34.4 mW under ±11-V bipolar HV supplies for sampling network and 1.8-V supply for the core circuits, corresponding to a FoMs of 175.4 dB, respectively. The entire chip occupies 7.2-mm² area.