A 128-way FPGA platform for the acceleration of KLMS algorithm

Xiaowei Ren; Qihang Yu; Badong Chen; Nanning Zheng; Pengju Ren

doi:10.1109/ASPDAC.2015.7058925

A 128-way FPGA platform for the acceleration of KLMS algorithm

Xiaowei Ren
, Qihang Yu
, Badong Chen
, Nanning Zheng
, Pengju Ren

Xi'an Jiaotong University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper proposes a 128-way parallel FPGA platform to accelerate the kernel least mean square (KLMS) algorithm. With the adoption of a quantized method and pipeline technology, this platform which works at 200MHz is 4827 times faster, on average, than the Matlab code running on a 3GHz Intel(R) Core(TM) i5-2320 CPU.

Original language	English
Title of host publication	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	18-19
Number of pages	2
ISBN (Electronic)	9781479977925
DOIs	https://doi.org/10.1109/ASPDAC.2015.7058925
State	Published - 11 Mar 2015
Event	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan Duration: 19 Jan 2015 → 22 Jan 2015

Publication series

Name	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Conference

Conference	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Country/Territory	Japan
City	Chiba
Period	19/01/15 → 22/01/15

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10.1109/ASPDAC.2015.7058925

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Ren, X., Yu, Q., Chen, B., Zheng, N., & Ren, P. (2015). A 128-way FPGA platform for the acceleration of KLMS algorithm. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 18-19). Article 7058925 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7058925

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title = "A 128-way FPGA platform for the acceleration of KLMS algorithm",

abstract = "This paper proposes a 128-way parallel FPGA platform to accelerate the kernel least mean square (KLMS) algorithm. With the adoption of a quantized method and pipeline technology, this platform which works at 200MHz is 4827 times faster, on average, than the Matlab code running on a 3GHz Intel(R) Core(TM) i5-2320 CPU.",

author = "Xiaowei Ren and Qihang Yu and Badong Chen and Nanning Zheng and Pengju Ren",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 ; Conference date: 19-01-2015 Through 22-01-2015",

year = "2015",

month = mar,

day = "11",

doi = "10.1109/ASPDAC.2015.7058925",

language = "英语",

series = "20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "18--19",

booktitle = "20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015",

}

Ren, X, Yu, Q, Chen, B , Zheng, N & Ren, P 2015, A 128-way FPGA platform for the acceleration of KLMS algorithm. in 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015., 7058925, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 18-19, 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, 19/01/15. https://doi.org/10.1109/ASPDAC.2015.7058925

A 128-way FPGA platform for the acceleration of KLMS algorithm. / Ren, Xiaowei; Yu, Qihang; Chen, Badong et al.
20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 18-19 7058925 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Ren, Pengju

PY - 2015/3/11

Y1 - 2015/3/11

N2 - This paper proposes a 128-way parallel FPGA platform to accelerate the kernel least mean square (KLMS) algorithm. With the adoption of a quantized method and pipeline technology, this platform which works at 200MHz is 4827 times faster, on average, than the Matlab code running on a 3GHz Intel(R) Core(TM) i5-2320 CPU.

AB - This paper proposes a 128-way parallel FPGA platform to accelerate the kernel least mean square (KLMS) algorithm. With the adoption of a quantized method and pipeline technology, this platform which works at 200MHz is 4827 times faster, on average, than the Matlab code running on a 3GHz Intel(R) Core(TM) i5-2320 CPU.

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M3 - 会议稿件

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T3 - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

SP - 18

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BT - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Y2 - 19 January 2015 through 22 January 2015

ER -

A 128-way FPGA platform for the acceleration of KLMS algorithm

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