A 1.2-mA Fast-Charge Input Buffer with CLS for 4-MS/s SC Oversampling ADC Achieving +1-2.5-ppm/FSR INL

  • Yang Chen
  • , Binyu Cai
  • , Changhuan Chen
  • , Quan Sun
  • , Xiaofei Wang
  • , Hong Zhang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper presents a 1.2-mA fast-charge input buffer with correlated level shifting (CLS) for a 4-MS/s SC oversampling ADC fabricated in 180-nm CMOS. The buffer includes a separate closed-loop fast charger to avoid the slewing process before the fine settling and CLS to confine the OTA's output into a small voltage range for linearity improvement with acceptable power consumption. The ADC with the buffer achieves 103.4-dB SNDR, 113.2-dB SFDR, and +/-2.5-ppm/FSR INL under 4-MS/s fs.

Original languageEnglish
Title of host publicationProceedings of 2023 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages105-107
Number of pages3
ISBN (Electronic)9798350344288
DOIs
StatePublished - 2023
Event2023 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2023 - Hefei, China
Duration: 27 Oct 202329 Oct 2023

Publication series

NameProceedings of 2023 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2023

Conference

Conference2023 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2023
Country/TerritoryChina
CityHefei
Period27/10/2329/10/23

Keywords

  • CLS
  • fast-charge
  • input buffer
  • oversampling ADC

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