TY - GEN
T1 - A 12-bit 100MS/s SAR ADC with digital error correction and high-speed LMS-based background calibration
AU - Lan, Zhechong
AU - Dong, Li
AU - Jing, Xixin
AU - Geng, Li
N1 - Publisher Copyright:
© 2021 IEEE
PY - 2021
Y1 - 2021
N2 - ADC is a significant block in wireless systems, which requires high bandwidth of hundreds of MHz and high resolution of 12-bits. Successive-approximation register (SAR) ADC is an energy efficient architecture but its conversion speed is generally restricted. This paper proposed a scheme to enhance the speed and lower the power consumption of the Least Mean Square (LMS) background calibration, so that it can be used in the design of high-speed SAR ADC. The DEC technique is designed based on the non-binary search, which tackles the insufficient DAC settling, so the conversion speed can be enhanced. Furthermore, the LMS-based background calibration can also improve the linearity of the ADC, so the accuracy of the SAR ADC increases. The proposed SAR ADC is designed in a standard 55 nm CMOS technology with a core area of 0.08 mm2. It consumes 3.59 mW at 100 MS/s sampling rate, achieving a SNDR of 66.78 dB. A good figure of merit (FoM) of 20.13 fJ/conversion-step is obtained.
AB - ADC is a significant block in wireless systems, which requires high bandwidth of hundreds of MHz and high resolution of 12-bits. Successive-approximation register (SAR) ADC is an energy efficient architecture but its conversion speed is generally restricted. This paper proposed a scheme to enhance the speed and lower the power consumption of the Least Mean Square (LMS) background calibration, so that it can be used in the design of high-speed SAR ADC. The DEC technique is designed based on the non-binary search, which tackles the insufficient DAC settling, so the conversion speed can be enhanced. Furthermore, the LMS-based background calibration can also improve the linearity of the ADC, so the accuracy of the SAR ADC increases. The proposed SAR ADC is designed in a standard 55 nm CMOS technology with a core area of 0.08 mm2. It consumes 3.59 mW at 100 MS/s sampling rate, achieving a SNDR of 66.78 dB. A good figure of merit (FoM) of 20.13 fJ/conversion-step is obtained.
KW - Analog to digital converter (ADC)
KW - Digital error correction
KW - LMS-based background calibration
KW - Successive approximation register (SAR)
UR - https://www.scopus.com/pages/publications/85108992758
U2 - 10.1109/ISCAS51556.2021.9401172
DO - 10.1109/ISCAS51556.2021.9401172
M3 - 会议稿件
AN - SCOPUS:85108992758
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Y2 - 22 May 2021 through 28 May 2021
ER -