A 112Gb/s low-noise PAM-4 linear optical receiver in 28nm CMOS

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

A 112Gb/s PAM-4 linear optical receiver with low noise, high linearity in 28nm CMOS is presented. The receiver signal chain consists of a transimpedance amplifier (TIA), a continuous time linear equalizer (CTLE), a variable gain amplifier (VGA), and an output buffer. PMOS CML logic is used based on the device characteristics. The low-noise topology and novel gain control techniques together enable state-of-the-art performance. The receiver achieves 2.72\mu Arms input-referred noise current, 71dB \Omega transimpedance gain and 37 GHz bandwidth. It is able to provide 18.5dB dynamic range to support maximum input overload current of 1.8mApp. The total harmonica distortion (THD) is below 5% under 660mVpp output swing. This receiver consumes 96.8mW from 1.5V supply.

Original languageEnglish
Title of host publication2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728102863
DOIs
StatePublished - Jun 2019
Event2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019 - Xi'an, China
Duration: 12 Jun 201914 Jun 2019

Publication series

Name2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019

Conference

Conference2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019
Country/TerritoryChina
CityXi'an
Period12/06/1914/06/19

Keywords

  • 112Gb/s
  • 28nm CMOS
  • Linear optical receiver
  • Low noise
  • Low power
  • Negative capacitance
  • PAM-4

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