A 100 MHz, 0.8-to-1.1 V, 170 mA Digital LDO with 8-Cycles Mean Settling Time and 9-Bit Regulating Resolution in 180-nm CMOS

This brief presents an all-digital low dropout regulator (DLDO) with high regulating resolution and fast transient tracking by combining novel interval-searching algorithm and recover acceleration techniques. By bringing forth an enhanced interval-searching algorithm (ISA) with 9-bit register regulating precision, the output can be stabilized within 8 cycles when the load changes. A recover acceleration (RA) technique is proposed to improve the transient response and stability. The DLDO is fabricated with standard 180-nm CMOS process. The proposed DLDO needs 390 pF output capacitance and can provide as much as 170 mA load current. The measured load regulation is 0.11 mV/mA at 0.9 V output with 160 mA load current range. The maximum current efficiency is up to 99.71%. The two FOMs of 2.03 ps and 0.362 pF are also achieved to illustrate the merits of this design.