A 0.71-pJ/bit 64-Gb/s PAM-4 CDR Using a Charge-Calculated-Linear Phase Detector Achieving 12MHz JTOL@1UI and 361fs Recovered Clock in 28nm CMOS

Runchen Wang; Lingao Huang; Yu Lv; Ya Zhao; Guohe Zhang; Li Geng; Pui In Mak; Chao Fan

doi:10.1109/CICC65509.2026.11509585

A 0.71-pJ/bit 64-Gb/s PAM-4 CDR Using a Charge-Calculated-Linear Phase Detector Achieving 12MHz JTOL_@1UI and 361fs Recovered Clock in 28nm CMOS

Runchen Wang
, Lingao Huang
, Yu Lv
, Ya Zhao
, Guohe Zhang
, Li Geng
, Pui In Mak
, Chao Fan

Xi'an Jiaotong University
University of Macau

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper reports a 64 Gb/s PAM-4 CDR incorporating a charge-calculated-linear phase detector (CCL-PD) to maintain the superior jitter tolerance (JTOL) and low-jitter recovered clock simultaneously. Specifically, the CCL-PD facilitates sensing all PAM-4 data transitions and maintains a uniform locking point, which benefits not only high gain but also reduced recovered clock jitter. The inherent ×4 frequency multiplication in tiny multi-phase injection-locking ring oscillator (MP-ILRO) helps a half-rate recovered clock. Prototyped in 28-nm CMOS, the 64 Gb/s PAM-4 CDR occupies 0.016 mm² and achieves JTOL_@1UI at 12-MHz frequency with a bit efficiency of 0.71 pJ/bit. The recovered 4 GHz and 16 GHz clocks score 361 fs and 388 fs jitter, respectively.

Original language	English
Title of host publication	2026 IEEE Custom Integrated Circuits Conference, CICC 2026 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798331572105
DOIs	https://doi.org/10.1109/CICC65509.2026.11509585
State	Published - 2026
Externally published	Yes
Event	46th Annual IEEE Custom Integrated Circuits Conference, CICC 2026 - Seattle, United States Duration: 19 Apr 2026 → 23 Apr 2026

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Conference

Conference	46th Annual IEEE Custom Integrated Circuits Conference, CICC 2026
Country/Territory	United States
City	Seattle
Period	19/04/26 → 23/04/26

Keywords

charge-calculated-linear phase detector (CCL-PD)
clock jitter
ISI
jitter tolerance (JTOL)
multi-phase injection locking ring oscillator (MP-ILRO)
PAM-4 clock and data recovery (CDR)

Access to Document

10.1109/CICC65509.2026.11509585

Cite this

Wang, R., Huang, L., Lv, Y., Zhao, Y., Zhang, G., Geng, L., Mak, P. I., & Fan, C. (2026). A 0.71-pJ/bit 64-Gb/s PAM-4 CDR Using a Charge-Calculated-Linear Phase Detector Achieving 12MHz JTOL_@1UI and 361fs Recovered Clock in 28nm CMOS. In 2026 IEEE Custom Integrated Circuits Conference, CICC 2026 - Proceedings (Proceedings of the Custom Integrated Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC65509.2026.11509585

Wang, Runchen ; Huang, Lingao ; Lv, Yu et al. / A 0.71-pJ/bit 64-Gb/s PAM-4 CDR Using a Charge-Calculated-Linear Phase Detector Achieving 12MHz JTOL_@1UI and 361fs Recovered Clock in 28nm CMOS. 2026 IEEE Custom Integrated Circuits Conference, CICC 2026 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2026. (Proceedings of the Custom Integrated Circuits Conference).

@inproceedings{34a514bebf7e4c9593b504d6727f4ed7,

title = "A 0.71-pJ/bit 64-Gb/s PAM-4 CDR Using a Charge-Calculated-Linear Phase Detector Achieving 12MHz JTOL@1UI and 361fs Recovered Clock in 28nm CMOS",

abstract = "This paper reports a 64 Gb/s PAM-4 CDR incorporating a charge-calculated-linear phase detector (CCL-PD) to maintain the superior jitter tolerance (JTOL) and low-jitter recovered clock simultaneously. Specifically, the CCL-PD facilitates sensing all PAM-4 data transitions and maintains a uniform locking point, which benefits not only high gain but also reduced recovered clock jitter. The inherent ×4 frequency multiplication in tiny multi-phase injection-locking ring oscillator (MP-ILRO) helps a half-rate recovered clock. Prototyped in 28-nm CMOS, the 64 Gb/s PAM-4 CDR occupies 0.016 mm2 and achieves JTOL@1UI at 12-MHz frequency with a bit efficiency of 0.71 pJ/bit. The recovered 4 GHz and 16 GHz clocks score 361 fs and 388 fs jitter, respectively.",

keywords = "charge-calculated-linear phase detector (CCL-PD), clock jitter, ISI, jitter tolerance (JTOL), multi-phase injection locking ring oscillator (MP-ILRO), PAM-4 clock and data recovery (CDR)",

author = "Runchen Wang and Lingao Huang and Yu Lv and Ya Zhao and Guohe Zhang and Li Geng and Mak, \{Pui In\} and Chao Fan",

note = "Publisher Copyright: {\textcopyright} 2026 IEEE.; 46th Annual IEEE Custom Integrated Circuits Conference, CICC 2026 ; Conference date: 19-04-2026 Through 23-04-2026",

year = "2026",

doi = "10.1109/CICC65509.2026.11509585",

language = "英语",

series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2026 IEEE Custom Integrated Circuits Conference, CICC 2026 - Proceedings",

}

Wang, R, Huang, L, Lv, Y, Zhao, Y, Zhang, G, Geng, L, Mak, PI & Fan, C 2026, A 0.71-pJ/bit 64-Gb/s PAM-4 CDR Using a Charge-Calculated-Linear Phase Detector Achieving 12MHz JTOL_@1UI and 361fs Recovered Clock in 28nm CMOS. in 2026 IEEE Custom Integrated Circuits Conference, CICC 2026 - Proceedings. Proceedings of the Custom Integrated Circuits Conference, Institute of Electrical and Electronics Engineers Inc., 46th Annual IEEE Custom Integrated Circuits Conference, CICC 2026, Seattle, United States, 19/04/26. https://doi.org/10.1109/CICC65509.2026.11509585

A 0.71-pJ/bit 64-Gb/s PAM-4 CDR Using a Charge-Calculated-Linear Phase Detector Achieving 12MHz JTOL_@1UI and 361fs Recovered Clock in 28nm CMOS. / Wang, Runchen; Huang, Lingao; Lv, Yu et al.
2026 IEEE Custom Integrated Circuits Conference, CICC 2026 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2026. (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Wang, Runchen

AU - Huang, Lingao

AU - Lv, Yu

AU - Zhao, Ya

AU - Zhang, Guohe

AU - Geng, Li

AU - Mak, Pui In

AU - Fan, Chao

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N2 - This paper reports a 64 Gb/s PAM-4 CDR incorporating a charge-calculated-linear phase detector (CCL-PD) to maintain the superior jitter tolerance (JTOL) and low-jitter recovered clock simultaneously. Specifically, the CCL-PD facilitates sensing all PAM-4 data transitions and maintains a uniform locking point, which benefits not only high gain but also reduced recovered clock jitter. The inherent ×4 frequency multiplication in tiny multi-phase injection-locking ring oscillator (MP-ILRO) helps a half-rate recovered clock. Prototyped in 28-nm CMOS, the 64 Gb/s PAM-4 CDR occupies 0.016 mm2 and achieves JTOL@1UI at 12-MHz frequency with a bit efficiency of 0.71 pJ/bit. The recovered 4 GHz and 16 GHz clocks score 361 fs and 388 fs jitter, respectively.

AB - This paper reports a 64 Gb/s PAM-4 CDR incorporating a charge-calculated-linear phase detector (CCL-PD) to maintain the superior jitter tolerance (JTOL) and low-jitter recovered clock simultaneously. Specifically, the CCL-PD facilitates sensing all PAM-4 data transitions and maintains a uniform locking point, which benefits not only high gain but also reduced recovered clock jitter. The inherent ×4 frequency multiplication in tiny multi-phase injection-locking ring oscillator (MP-ILRO) helps a half-rate recovered clock. Prototyped in 28-nm CMOS, the 64 Gb/s PAM-4 CDR occupies 0.016 mm2 and achieves JTOL@1UI at 12-MHz frequency with a bit efficiency of 0.71 pJ/bit. The recovered 4 GHz and 16 GHz clocks score 361 fs and 388 fs jitter, respectively.

KW - charge-calculated-linear phase detector (CCL-PD)

KW - clock jitter

KW - ISI

KW - jitter tolerance (JTOL)

KW - multi-phase injection locking ring oscillator (MP-ILRO)

KW - PAM-4 clock and data recovery (CDR)

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DO - 10.1109/CICC65509.2026.11509585

M3 - 会议稿件

AN - SCOPUS:105040903844

T3 - Proceedings of the Custom Integrated Circuits Conference

BT - 2026 IEEE Custom Integrated Circuits Conference, CICC 2026 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 46th Annual IEEE Custom Integrated Circuits Conference, CICC 2026

Y2 - 19 April 2026 through 23 April 2026

ER -

Wang R, Huang L, Lv Y, Zhao Y, Zhang G, Geng L et al. A 0.71-pJ/bit 64-Gb/s PAM-4 CDR Using a Charge-Calculated-Linear Phase Detector Achieving 12MHz JTOL_@1UI and 361fs Recovered Clock in 28nm CMOS. In 2026 IEEE Custom Integrated Circuits Conference, CICC 2026 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2026. (Proceedings of the Custom Integrated Circuits Conference). doi: 10.1109/CICC65509.2026.11509585