统一计算架构下的装配精度并行计算模型

Aiming at the low computing efficiency of assembly accuracy for complex assemblies under multi-index requirements, a parallel computing model for assembly accuracy with multiple error transmission paths based on the compute unified device architecture (CUDA) was proposed. Firstly, the torsor transformation was performed on the local parallel structure to obtain the SDT model covering the series and parallel structures. On this basis, the assembly feature was used as the error transfer unit to build the position transformation and error transfer model, decompose the error transfer process, and provide support for the subsequent parallel computing. Next, based on the type characteristics of the error transfer path of the multiple functional requirements (FRs), the path was combined and the error torsor was reused to reduce the amount of computation and data generation. Finally, the algorithm data structure was designed to allocate thread tasks according to task requirements, reasonably allocate memory and reduce memory access delay. The model was used to simulate the assembly accuracy of the high pressure compressor rotor of an aeroengine, and the simulation results showed that the proposed model could compute the assembly accuracy about 97. 3 times faster than a conventional CPU model and can provide support for the assembly accuracy computation and tolerance design of complex assemblies.